Prior to PCI-Express introduction, hotplug of system, chassis and other components were mainly implemented using proprietary HW. This requires custom HW, Firmware and OS drivers update which are quite messy and prone to various errors/bugs etc. However with introduction of PCISIG standard, entire hotplug operation from HW to Operating System are quiet trivial eliminating proprietary implementation.
On any modern systems, typically you've Root Complex and/or PCI-Express switch connected to CPU. These devices have about 40-80 "x1" PCI Express lanes and can be grouped in units of "x4", "x8" or "x16" lanes. Out of these lanes, only limited lanes or ports can function as PCI Hotplug capable slot. The reason being PCI-E hotplug need about 10+ external discrete signals to function properly. For obvious reasons, not all lanes or ports can function as hotplug due to limited pins in the Root Complex/Switch.
Some of the important hotplug signals are PERST, PRSNT1/2, PWRFLT, MRL and BUTTON. Following diagram below identifies flow of above signals with respect to hot plug devices. All PCI ports supporting hotplug need to implement "Slot capabilities" register space accessible to CPU. This space provides CPU to query whether hotplug device are present, quiesce the bus interface, max power for this slot and whether user has initiated any operation on the hotplug device. Standard hotplug devices typically have BLUE OK2RM, FAULT visual indicators and Attention Button to configure the device. User can press Attention Button and wait until BLUE OK2RM LED is lit before the device can be removed safely. Since PCI-Express is a chatty protocol, surprise removal of hotplug device will result in system panic.
In next blog, I'll discuss on how Operating System (Solais/Linux) and HW work together to configure and unconfigure hotplug devices.
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